Parallel Input Serial Output Shift Register Verilog Code
Parallel Input Serial Output Shift Registers
Sorry and I thank you all, As the old proverb goes; 'Sometimes it's hard to see the forest from the trees' There was nothing wrong with the verilog code (except for the blocking statement) the actual problem turned out to be a USB serial analyzer that was tied into the serial line to the CPLD to monitor the serial stream, unfortunately the analyzer was unplugged from the usb port, or otherwise upowered while everything else was running and created some very interesting artifacts, once the logic analyzer was again connected to the usb port, everything worked flawlessly.